1. Technical Field
The present invention relates to the packaging of integrated circuit chips; and more particularly, to a package for a microelectronic integrated circuit chip and method of fabrication.
2. Background Art
Integrated circuit (IC) chips of extremely small size are typically mounted in the central portion of a support structure or package that includes closely-spaced metallic paths or leads for electrical connection to similarly spaced metallic terminals of the IC chip. The closely spaced metallic leads of the package extend from a point adjacent the mounted chip and fan outwardly in a direction away from the chip to terminate in bonding pads or lead wires that are suitably spaced for connection to test and burn-in apparatus for the IC chip. The size, number and proximity of the bonding connections of the IC chip determine the overall size of the package. The greater the number of leads of the package, the greater the required length of the outwardly extending leads in order to obtain the proper spacing of the bonding pads or lead wires used for burn-in and test connections. This problem was minimized as discussed in my U.S. Pat. No. 4,730,232 dated Mar. 8, 1988, and as pointed out in the patent, after the testing and burning-in of the mounted integrated circuit chip, the package is scribed by a laser along a line adjacent where the metallic paths begin their fanning out. The package is snapped apart along the laser scribe resulting in a smaller package. Thus, the resulting small package would have closely spaced bonding pads for wire bonding to the next level of interconnect, such as a printed circuit board, for example.
Although suitable for the purposes intended, the discussion of the IC package in the above identified U.S. Pat. No., disclosed power, ground, and signal path leads which were limited with respect to the type of chip construction and power and ground requirements.